RISC processors are designed to perform a smaller number of types of computer instruction so that they can operate at a higher speed (perform more million instructions per second, or millions of instructions per second). Since each instruction type that a computer must perform requires additional transistors and circuitry, a larger list or set of computer instructions tends to make the processor more complicated and slower in operation.
RISC processors in general are self-initiating devices. That is they have the ability to initialize their internal state and begin a process thread in a deterministic fashion. RISC processors have two essential mechanisms, a means by which control information (i.e. RISC instructions) are fetched from a memory and applied to the RISC processor, and a means by which data items are imported and exported from the RISC processor itself.
Typically, process threads are begun when an event response is required. The thread begins by placing the RISC processor into a known state. In the known state, all applicable internal registers are set to an initial state to produce a deterministic result. This process of initialization is directed and controlled by the RISC processor. When the initialization completes, the response to the event begins. The combination of RISC directed initialization and process thread processing comprises the total compute load for an event response. In effect the RISC processor has to perform two serial tasks, initialization and execution of the process thread.
RISC processors generally initialize their process state by sequencing through a set of instructions. The set of instructions set the internal registers to desired values prior to executing a process thread. This self-configuring initialization process requires the RISC processor to consume time (compute cycles or compute bandwidth, not to mention memory bandwidth) to setup or to initialize the process thread. For real time short duration applications, the overhead of process state initialization may be longer than the execute duration of the real time application itself. This diminishes the effectiveness of the RISC processor.